Immittance network incorporating one negative resistance

ABSTRACT

Circuits realizing decomposable bi-order-n impedance and admittance functions in which the impedance function is realized by a single tee section terminated in a positive impedance and has a series positive and negative branch resistance and a shunt positive resistance and positive impedance interposed between the series branch elements. The admittance function is realized by a pi section terminated in a positive admittance having a series branch composed of the parallel combination of a positive conductance and a positive admittance and having two shunt branches, one being a positive resistance and the other a negative resistance.

United States Patent 72] Inventor Kurt H. l-laase Wateitown, Mass. [211App]. No. 702,890

[22] Filed Feb. 5, 1968 [45] Patented Mar. 23, 1971 [73] Assignee TheUnited States of America as represented by the Secretary of the AirForce [54] IMMITTANCE NETWORK INCORPORATING ONE [56] References CitedOTHER REFERENCES Weinberg, L., Network Analysis and Synthesis McGrawHill, 1962, TK 3226 W4 pp 43l 442 Primary ExaminerHerman Karl SaalbachAssistant Examiner-Wm. N. Punter Attorneys-Harry A. Herbert, Jr. andJulian L. Siegel ABSTRACT: Circuits realizing decomposable bi-order-nimpedance and admittance functions in which the impedance function isrealized by a single tee section terminated in a positive impedance andhas a series positive and negative branch resistance and a shuntpositive resistance and positive impedance interposed between the seriesbranch elements. The admittance function is realized by a pi sectiontenninated in a positive admittance having a series branch composed ofthe parallel combination of a positive conductance and a positiveadmittance and having two shunt branches, one being a positiveresistance and the other a negative resistance.

Mo -Fame; 6/20 (/17 IMMITTANCE NETWORK INCORPORATING ONE NEGATIVERESISTANCE BACKGROUND OF THE INVENTION This invention relates to adriving point immittance network and more particularly to a one portnetwork that is a canonical circuit representing a positive realbi-order-n immittance function in which resistance is the only negativeelement.

In my previously filed application, now issued US. Pat. No. 3,479,618,there was disclosed a network realizing the biorder-n immittancefunction which uses negative impedance whereas the present invention isa circuit utilizing negative resistance which has the advantage in thatthe negative element is not dependent upon frequency.

A novel technique is presented to realize an immittance functionpresented by the analytical expression of Equation (1). The termimmittance is of a neutral character and can be deliberately interpretedas impedance or admittance. Since a canonical network is presented, theleast amount of space and weight is required, which is advantageous inmany applications.

SUMMARY OF THE INVENTION A bi-order-n function is where two polynomialsof the same even order n are divided. If F (s) is positive real, then ingeneral none of the coefficients N and D, in the sequence inl ismissing. The necessary and sufficient conditions for positive realnessof F (s) are well known and are referred to by Otto Brune in the Journalof Mathematics and Physics, Volume 10, pp l9l236, Aug. 1931.

The present invention is mainly concerned with two circuits, one interms of impedance and the other in terms of admittance. Both circuitshave the same driving point immittance F(s) and are dual in the sensethat the impedance circuit has the driving point impedance Z(s)=(s) andthe admittance circuit has the driving point admittance ff (s)=F (s) andboth circuits us e negative resistances.

The function of F (s) is The only difference between Equation (2) andEquation l) is the use of bars over the capital letters. By this meanswe indicate that F(s) is a particular bi-order-n function furtherreferred to as a decomposable bi-order-n function." It can be obtainedfrom any positive real bi-order-n function F (s) according to F=F(s2-K[F,,,(s)]. (3) where F(s) and F(s) are of the same rank 2n (both' arebiorder-n functions), F ,,,(s) is a suitable"pos' 1 tive real function,and K is a positive constant that normalizes F (s).

It is therefore an object to provide a novel canonical driving-pointnetwork.

It is another object to provide a canonical driving-point network thatrepresents a bi-order-n function.

It is still another object to provide a driving-point networkrepresenting a bi-order-n function in terms of impedances andadmittances where negative elements are resistive.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of acanonical one port network using negative impedance;

FIG. 2 is a circuit diagram of a canonical one port network usingnegative admittance;

FIG. 3 shows an embodiment of an invention in which a canonical one portnetwork uses a negative resistance;

FIG. 4 shows the second embodiment of the invention in which a canonicalone port network uses a negative conductance;

FIG. 5 shows a variation of that network shown in FIG. 3;

FIGS. 6A and 6B show the circuit elements that can be used when thecircuit is represented in terms of impedances; and

FIGS. 7A and 7B show the circuit elements that can be used when thecircuit is represented in terms of admittances.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is anetwork that has a driving-point immittance function In my previouslyfiled application, the network shown in FIGS. 1 and 2 was described.Necessarily in these circuits the immittance W is negative in bothcircuits.

The cirguits of FIG. 1 and FIG. 2 have the driving-point impedance F(s). Both circuits are dual in the sensg that the circuit of FIG. 1 hasa driving-point impedance Z(s)=F(s) and the circuit of FIG. 2 has thedriving-point admittance of I (sFFYs): Because of this duality, thediscussion is mainly with reference to the circuit of FIG. 1 buteverything holds true for the dual circuit of FIG. 2. g

Shown in FIG. 1 is impedance network 9 having a single T section that isterminated with resistance 13 and of magnitude #z where z is thepositive constant and the network is driven by source 11. The T hasseries branch impedances U and W, where U is a positive and W is anegative impedance. The T also has a shunt branch that is composed ofpositive impedances V and X and has the driving-point impedance Z(s)= F(s).

Shown in FIG. 2 is admittance network 10 having a single pi section thatis terminated with conductance 14 of the magnitude Z=z where z is againa positive constant and the network is driven by source ll. The pi hasshunt branch admittances U and W, where U is a positive and W is anegative admittance and has a series branch that is composed of positiveadmitta nces V and X. The pi circuit has the driving-point impedance I(s)=F(s).

Let

W=- (u-l) )/n=w where v is positive, g also positive and greater than I,then l/u+l/v+l/w=0 (6) and u=v(gl is positive and w=-v(gl )I isnegative. Hence Wis negative. Let @(s) be a normalized and positive realfunction of the kind s -l-qm1s .+a1s+a0 ago I (7) s +b s .+b s+b b(s)'In equation (7) the order m is any integer l, 2, m. Let

=x P where x is a positive constant and I5(s) is a positive real andnormalized function of the same rank as 1 (s), but of the form Thedriving-point immittances of the circuits in FIGS. 1 and 2 F39.

The highest power of s=o-+jw in the numerator and the denominator ofEquation I2) is 2m+2 since a(s) and a(s) are both polynomials of theorder m.

The immittances U, V, and Wimply the same function (8) sir-g3 (14) and implies (F(s) 52? (14a) a(s), b(s), a(s) and B(s) are normalizedpolynomials of the order m (any integer) and The v, x, and r 1 inEquation (12) are positive constants which can be computed for F (s)given in the form of Equation (2). Also the functions (s) and @(s) canbe computed so t hat the circuit in FIG. 1 for the impedanceinterpretation of F (s) and/or the circuit in FIG. 2 for the admittanceinterpretation can be constructed.

When m=l, the following circuit elements are applicable. The impedancecircuit implying the function (s) which equals s b is shown in FIG. 6A.This circuit comprises inductor 31 in series with the parallelcombination of inductor 33 and resistor 35. The impedance circuitimplying is shown in FIG. 6B. The circuit comprises capacitor 41 inparallel with the series combination of capacitor 37 and resistor 39.The admittance circuit implying the function i m i s b is shown in FIG.7A in which capacitor 47 is in parallel with the series combination ofcapacitor 43 and resistor 45. The admittance function implying I ""jf5+3, 43(8) 5 8 +0: is shown in FIG. 7B, which comprises inductor 49 inseries with the parallel combination of inductor 51 and resistor 53.

The following transformation of the expression on the right side ofEquation (12) is now performed; new constants x, n, z and R' areintroduced. a(s), b(s), (IQ), and ,B(s) remain, and the following isobtained:

Then Equations (l6), (l2), and (16a) and (13) can be compared in theircoefficients and we obtain:

Instead of the circuits in FIGS. 1 and 2 we now obtain impedance circuit15 and admittance circuit 16 shown in FIGS. 3 and 4 respectively. Theyhave the same driving-point immittances. The immittances X and x fls)imply the same frequency function @(s), only the positive constants aredifferent; they are x in FIG. 1 and x in FIG. 3. The immittances U, V,Win FIG. 1 and zl (s) in FIG. 3 imply the same frequency function F(s),only the constants are different. There is only one such immittance inthe circuit in FIG. 3 and the negative immittance in FIG. 1 disappearscompletely. Instead, the circuit in FIG. 3 implies three resistances 1Rul=Rvl 1" E (21a) R.. Rv( -1)/l'= ,fi (21b) and R is given by Equation(20).

In F124,; U, V and W imply. the frequency:function p;.X implies I and Zimplies a dummy function, Z=z. If we interchange the frequency function(p with a dummy function, and leave I as it is, then FIG. 3 is obtainedwhere the dummy function is implied. R' R' and R',, are implied in thetermination and (,0 remains the same. The driving. point impedanceremains in variant provided the prime constants have been calculatedaccording to equations (17) to (20). The resistance R' is negative sincey l. It can be realized in any way that realizes a negative resistance;for instance, as in the form of a tunnel-diode. It is an essentialfeature that the elements in the circuit be arranged such that thenegative resistance is at ground level, which is shown in impedancecircuit 17 of FIG. 5 which is essentially identical with FIG. 3. FIGS. 2and 4 are dual circuits of that shown in FIGS. 1 and 3 and the conceptof duality applies.

lclaim:

l. A one port impedance network representing the bi-ordern function thenetwork comprising:

a. a driving source having first and second terminals;

b. a first positive resistance connected to the first terminal of thedriving source and equal to 1/11 where n equals the square root of thereciprocal of the magnitude of the terminating resistance;

c. a negative resistance equal to (1 1 2 connected to the first positiveresistance; d. a second positive resistance equal to 1 1 1 I: 2 z n 1)11/15, and -l- 0121 IS defined implicitly by =0 where u=v(n1) u v w andw: v

F(s) 8 +N -1S -i"N 8+No s +D s' +D s+D the network comprising:

a. a driving source having first and second terminals;

b. a first positive conductance equal to 1/ in parallel connection withthe driving source where g is equal to the square root of the reciprocalof the magnitude of the terminating conductance;

c. the parallel combination including a first positive admittance equalto x I (s) and a second positive conductance equal to the parallelcombination being connected to the first terminal of the driving source;

d. a negative conductance equal to 2 2 and connected to the parallelcombination and the second terminal of the driving source; and

e. a second admittance equal to z@(s) terminating the net- 1 work and inparallel connection with the negative conductance where 1 l 1 0] v 1sdefined lmpheitly by 5. A one port admittance network according to claim4 wherein I (s) comprises:

a. a first capacitor; and

b. a series combination including a second capacitor and a resistor inparallel connection with the first capacitor.

6. A one port admittance network according to claim 4 wherein I (s)comprises:

amst'inductor; and

b. a parallel combination including a second inductor and a resistor inseries connection with the first inductor.

1. A one port impedance network representing the bi-order-n function thenetwork comprising: a. a driving source having first and secondterminals; b. a first positive resistance connected to the firstterminal of the driving source and equal to 1/n where n equals thesquare root of the reciprocal of the magnitude of the terminatingresistance; c. a negative resistance equal to connected to the firstpositive resistance; d. a second positive resistance equal to connectedto the junction of the first positive resistance and the negativeresistance; e. a first impedance equal to x'' (s) having a seriesconnection with a second positive resistance and the second terminal ofthe driving source; and f. a second impedance equal to z'' phi (s)terminating the network in series with the negative impedance and inparallel with the second positive resistance and the first impedancewhere x'' x(n-1)2,
 2. A one port impedance network according to claim 1wherein phi (s) comprises: a. a first inductor; and b. a parallelcombination including a second inductor and a resistor in seriesconnection with the first inductor.
 3. A one port impedance networkaccording to claim 1 wherein (s) comprises: a. a first capacitor; and b.a series combination including a second capacitor and a resistor inparallel connection with the first capacitor.
 4. A one port admittancenetwork representing the bi-order-n function the network comprising: a.a driving source having first and second terminals; b. a first positiveconductance equal to 1/n in parallel connection with the driving sourcewhere n is equal to the square root of the reciprocal of the magnitudeof the terminating conductance; c. the parallel combination including afirst positive admittance equal to x'' (s) and a second positiveconductance equal to the parallel combination being connected to thefirst terminal of the driving source; d. a negative conductance equal toand connected to the parallel combination and the second terminal of thedriving source; and e. a second admittance equal to z'' phi (s)terminating the network and in parallel connection with the negativeconductance where
 5. A one port admittance network accoRding to claim 4wherein phi (s) comprises: a. a first capacitor; and b. a seriescombination including a second capacitor and a resistor in parallelconnection with the first capacitor.
 6. A one port admittance networkaccording to claim 4 wherein (s) comprises: a. a first inductor; and b.a parallel combination including a second inductor and a resistor inseries connection with the first inductor.